This invention relates generally to transmission of digital data, and more particularly concerns the transmission of digital data in scrambled fashion to facilitate clock recovery, recovery of the carrier through statistical techniques, and equalization of the number of "0"s and "1"s, thus eliminating the need for frequency response down to DC.
A common form of scrambler/descrambler data transmission system is based on a pseudo random sequence generator called a maximal length shift register. The maximal length shift register includes a shift register with exclusive OR feedback. The inputs to the exclusive OR gate feedback are connected to separate taps on the shift register. The maximal length shift register will clock through a pseudo random sequence, available at the output of the OR gate (input to shift register). The pseudo random sequence will repeat every 2.sup.N -1 clock cycles, where N is the number of stages in the shift register. The particular taps used for the inputs to the exclusive OR feedback gate must be carefully chosen to insure that the sequence is random and is of maximal length.
The maximal length shift register can be used to scramble data transmissions in two basic ways. The first, and most common, system is the self-synchronizing system in which a second OR gate is interposed in the feedback loop just before the input to the shift register. The second OR gate exclusively ORs the data with the feedback signal and produces the transmitter output at the input to the shift register. If the user data is held at a binary zero. the pseudo random generator performs exactly as if no data was present and that pseudo random sequence is connected to the transmission line. If, on the other hand, the user data is held at a binary one, a different pseudo random sequence is generated at the output of the OR gate (input to the shift register), and that sequence is connected to the transmission line. In general, the effect will be to randomize the data stream. Recovery of the original data is simplified by the fact that what is transmitted is the actual input to the shift register. By feeding the scrambled data received into a similar shift register with exclusive OR connections from the same shift register taps, the shift register generates the original transmit side pseudo random sequence on the receive side. This signal is then exclusively ORed with the scrambled data to restore the original data.
The second scrambling system is a synchronization system in which two free-running pseudo random sequence generators, each consisting of a maximal length shift register, are provided both at the transmit and receive end. The pseudo random sequence at the input of the shift register is then exclusively ORed with the data at the transmit end and connected to the transmission line. In addition, a synchronization signal is generated by the maximal length shift register which is also transmitted to the receive side. At the receive side, the synchronization signal is used to synchronize the freerunning maximal length shift register so that its output can then be exclusively ORed with the transmitted or scrambled data, thereby recovering the original data.
The second scrambling system has substantial advantages over the first system. Errors occurring in the transmission path of the first self synchronizing system show up immediately as the data is applied to the recovery exclusive OR gate. The transmission error propagates down the shift register past the exclusive OR taps. Consequently, one error in the transmission channel becomes N+1 separate errors in the maximal length shift register (where N equals the number of taps from the shift register). In the second system, errors in the transmission channel are only exclusively ORed with the pseudo random sequence which is unchanged, and therefore each transmission error only results in a single error in the data output.
Another difficulty in the transmission of binary data is the problem associated with demodulating binary phase shift keying data (BPSK). When BPSK data is received at a receiver and the receiver locks on to the carrier frequency and begins developing a carrier signal, there is 180.degree. uncertainty as to the absolute phase of the carrier. The result is that the demodulated data may either be inverted or not inverted. For quadrature phase shift keying (QPSK), there is a four-way ambiguity involving inversions of pairs of bits. Other modulation schemes such as M-ary PSK and M-ary QAM also produce phase ambiguities which must be resolved at the receiver. Commonly, such ambiguity is overcome by a system called differential encoding. Before transmission, binary "1"s are encoded as a change in state, and binary "0"s are encoded as no change in state. After demodulation, transitions are decoded to binary "1"s, and bits not causing a transition are decoded to binary "0"s. This process maintains correct polarity whether or not the transmission channel is inverted because it depends only on the change of state. Differential encoding, however, possesses its own problems in that it leads to a multiplication of errors, and each error propagates into two errors since each decoded bit depends on the current bit and the past bit to establish the change of state.